1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and the semiconductor device, particularly to a MOS (Metal Oxide Semiconductor) type field effect transistor.
2. Description of the Related Art
In recent years, for the purpose of enhancing the performance of transistors, impressing of a stress on a channel region so as to increase the drain current has been investigated. Examples of the stress impressing method include a method in which a highly stressed film is formed after the formation of a gate electrode so as to impress a stress on a channel region, and a process in which the source/drain regions of a P-channel MOS type field effect transistor (PMOSFET) are etched, and a silicon-germanium (SiGe) layer is epitaxially grown in the etched areas to exert a stress on a channel region.
The application of a stress to the channel region is more effective as the SiGe layer is closer to the channel region and as the volume of the SiGe layer is greater. Furthermore, while the source/drain regions are formed generally by ion implantation, addition of an impurity such as boron simultaneously with the epitaxial growth of the SiGe layer has also been investigated as a method of forming the source/drain regions of a PMOSFET (refer, for example, to JP-A-2002-530864, refer, particularly, to FIG. 4 and paragraph No. 0030).
Here, the above-mentioned method of manufacturing a PMOSFET will be described referring to FIGS. 4A to 4C. First, as shown in FIG. 4A, device isolation regions (omitted in the figure) are formed on the face side of a silicon substrate 11. Next, a gate electrode 13 is formed over the silicon substrate 11, with a gate insulating film 12 therebetween, and an offset insulating film 14 including a silicon nitride film is formed on the gate electrode 13. Subsequently, a silicon nitride film is formed over the silicon substrate 11 in the state of covering the gate insulating film 12, the gate electrode 13 and the offset insulating film 14, and the silicon nitride film is etched back by a dry etching method, whereby side walls 15 are formed on both lateral sides of the gate insulating film 12, the gate electrode 13 and the offset insulating film 14.
Next, as shown in FIG. 4B, the so-called recess etching, i.e., digging down the silicon substrate 11 by etching with the offset insulating film 14 and the side walls 15 as a mask, is conducted to form recess regions 16. Thereafter, a natural oxide film over the surface of the silicon substrate 11 is removed by a cleaning treatment using diluted hydrofluoric acid.
Subsequently, as shown in FIG. 4C, a silicon-germanium (SiGe) layer 17 containing a p-type impurity such as boron is epitaxially grown in the recess regions 16, i.e., on the surfaces of the dug-down portions of the silicon substrate 11. The SiGe layer 17 forms the source/drain regions, and the region, beneath the gate electrode 13 and located between the source/drain regions, of the silicon substrate 11 constitutes the channel region 18. The application of a stress to the channel region 18 by the SiGe layer 17 causes a straining (distortion) of the channel region 18, resulting in the formation of a PMOSFET having a sufficient carrier mobility.